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DM54155/DM74155 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and data applied at C2 is true through its outputs. The inverter following the C1 data input permits use as a 3-to-8-line decoder, or 1-to-8-line demultiplexer, without external gating. Input clamping diodes are provided on these circuits to minimize transmission-line effects and simplify system design. Features Applications: Dual 2-to-4-line decoder Dual 1-to-4-line demultiplexer 3-to-8-line decoder 1-to-8-line demultiplexer Individual strobes simplify cascading for decoding or demultiplexing larger words Input clamping diodes simplify system design Connection Diagram and Function Tables Dual-In-Line Package
2-Line-to-4-Line Decoder or 1-Line-to-4-Line Demultiplexer Inputs Outputs Select Strobe Data BA G1 C1 1Y0 1Y1 XX H X H H
1Y2 H
1Y3 H
LL LH HL HH XX Inputs Select BA XX LL LH HL HH XX
L L L L X
L L L L H
L H H H H Outputs
H L H H H
H H L H H
H H H L H
Strobe G2 H L L L L X
Data C2 X L L L L H
2Y0 H L H H H H
2Y1 H H L H H H
2Y2 H H H L H H
2Y3 H H H H L H
3-Line-to-8-Line Decoder or 1-Line-to-8-Line Demultiplexer Inputs Outputs Select Strobe-Or-Data (0) (1) (2) (3) CBA G 2Y0 2Y1 2Y2 2Y3 XXX H H H H H LLL L L H H H LLH L H L H H LHL L H H L H LHH L H H H L HLL L H H H H HLH L H H H H HHL L H H H H HHH L H H H H
(4) 1Y0 H H H H H L H H H
(5) 1Y1 H H H H H H L H H
(6) 1Y2 H H H H H H H L H
(7) 1Y3 H H H H H H H H L

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